With the current popularity of portable communication devices and developed semiconductor fabrication technology, high speed and high performance transistors are more densely integrated on semiconductor dies. Consequently, the amount of heat generated by the semiconductor dies increases significantly due to the large number of transistors integrated on the semiconductor dies, the large amount of power passing through the transistors, and the high operation speed of the transistors. Accordingly, it is desirable to package the semiconductor dies in a configuration for better heat dissipation.
Flip chip assembly technology is widely utilized in semiconductor packaging due to its preferable solder interconnection between flip chip dies and the laminate, on which the flip chip dies are mounted. The flip chip assembly technology eliminates the space needed for wire bonding and the die surface areas of a package, and essentially reduces the overall size of the package. In addition, the elimination of the wire bonding and implementation of a shorter electrical path from the flip chip dies to the laminate reduces undesired inductance and capacitance.
Further, semiconductor dies with silicon on insulator (SOI) structures are trending due to the low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. However, harmonic generations and low resistivity values of the SOI structures severely limit the SOI's usage in radio-frequency (RF) applications. By using SOI structures in RF fabrications, an interface between the silicon handle layer and an adjacent dielectric layer will generate unwanted harmonic and intermodulation products. Such spectrum degradation causes a number of significant system issues, such as unwanted generation of signals in other RF bands, which the system is attempting to avoid.
To accommodate the increased heat generation of high performance dies and to utilize the advantages of flip chip assembly, it is therefore an object of the present disclosure to provide an improved semiconductor package design with flip chip dies in a configuration for better heat dissipation. In addition, there is also a need to eliminate the deleterious effects of harmonic generations and intermodulation distortions.